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A high-performance, low cost inverse integer transform architecture for advanced video standard (AVS) video coding standard was presented. An 8×8 inverse integer transform is required in AVS video system which is compute-intensive. A hardware transform is inevitable to compute the transform for the real-time ap-plication. Compared with the 4×4 transform for H.264/AVC, the 8×8 integer transform is much more complex and the coefficient in the inverse transform matrix Ts is not inerratic as that in H.264/AVC. Dividing the Ts into matrix S8 and R8, the proposed architecture is implemented with the adders and the specific CSA-trees instead of multipliers, which are area and time consuming. The architecture obtains the data processing rate up to 8 pixels per-cycle at a low cost of area. Synthesized to TSMC 0.18 μm COMS process, the architecture attains the operating frequency of 300 MHz at cost of 34 252 gates with a 2-stage pipeline scheme. A reusable scheme is also introduced for the area optimization, which results in the operating frequency of 143 MHz at cost of only 19 758 gates. 相似文献
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This paper proposes an asynchronous complex pipeline based on ARM-V3 instruction set. Muller pipeline structure is used as prototype, and the factors which may affect pipeline performance are analyzed. To balance the difficulty of asynchronous design and performance analysis, both complete asynchronous and partial asynchronous structures aere designed and compared. Results of comparison with the well-Rnown industrial product ARM922T verify that about 30% and 40% performance improvement of the partial and complete asynchronous complex pipelines can be obtained respectively. The design methodologies can also be used in the design of other asynchronous pipelines. 相似文献
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