基于联合迭代译码的LDPC编码协作系统

为提高系统性能,提出了分别采用正规LDPC(low-density parity-check code)和非正规系统LDPC码的编码协作通信系统,并给出了用于源节点和中继点的双LDPC码的构造方法.导出了基于双LDPC码的总体校验矩阵,据此校验矩阵给出了相应的双层结构Tanner图,目的点采用基于该双层结构Tanner图的联合迭代译码新算法译码.理论分析和数值模拟表明,在相同条件下,理想LDPC编码协作系统的性能明显优于编码非协作系统的性能,当误比特率为10-5、译码迭代10次时,理想正规LDPC码和非正规系统LDPC码编码协作系统较相应的编码非协作系统分别具有1.0和0.6 dB增益.     

极化码SCS译码器的FPGA实现

随着通信技术的不断发展,极化码因其简洁的线性编码方式和优越的译码性能而在现代通信中占据重要地位,对极化码的译码器研究则具有极其重要的现实意义。论文研究极化码的编译码算法,并对SCS译码算法进行详细分析,提出了一种SCS译码器的FPGA实现方案。采用适于硬件实现的最小和算法和合理的量化方案,大胆提出双FIFO有序堆栈结构和单计算单元LLR计算结构的硬件设计,并设计合理的反馈模块以简化计算步骤。使用Verilog HDL语言在QuartusⅡ上进行模块编写后,调用Modelsim进行仿真,在系统时钟频率为600MHz的情况下,译码器的吞吐率可达12.49Mbps,资源利用率仅为4%。     

Accelerating BP-Based Iterative Low-Density Parity-Check Decoding by Modified Vertical and Horizontal Processes

Two modified BP algorithms related to vertical and horizontal processes are proposed to accelerate iterative low-density parity-check (LDPC) decoding over an additive white Gaussian noise (AWGN) channel, where the newly updated extrinsic information is immediately used in the current decoding round. Theoretical analysis and simulation results demonstrate that both the modified approaches provide significant performance improvements over the traditional BP algorithm with almost no additional decoding complexity. The proposed algorithm with modified horizontal process offers even better performance than another algorithm with the modified horizontal process. The two modified BP algorithms are very promising in practical communications since both can achieve an excellent trade-off between the performance and decoding complexity.