面向车载功能安全的低开销超标量双核锁步处理器架构设计

在车载功能安全领域，双核锁步架构是一种被广泛应用于解决处理器故障的冗余架构。为支持细粒度故障处理的超标量处理器提出一种新颖的双核锁步架构，通过以分支跳转指令的形式执行程序回滚，该架构能在故障发生的同一时钟周期内检测和纠正故障，且不需要额外的专用硬件模块来满足细粒度回滚的需求。还提出一种虚拟写回机制，该机制将特定数据传送到只读寄存器以防止故障衍生，使处理器无需在程序执行期间持续保存现场，从而显著节省了面积开销。试验结果表明，该架构对注入处理器的故障实现了较彻底的故障覆盖，对处理器原型的性能影响很小，与先前双核锁步相关的工作相比，时间和面积开销更小。

Design of a Low-Overhead Superscalar Dual-Core Lockstep Processor Architecture for Automotive Functional Safety

In the field of automotive functional safety, the dual-core lockstep (DCLS) architecture is a redundancy architecture widely used for addressing processor faults. This paper proposes a novel dual-core lockstep architecture for superscalar processors that supports fine-grained fault handling. By executing program rollback in the form of a branch instruction, the proposed architecture can detect and correct faults within the same clock cycle they occur, without the need for additional hardware support. Furthermore, the virtual writeback (VW) mechanism is also presented, which feeds specific data to read-only registers to prevent fault propagation. This allows the processor to avoid continuous context saving during program execution, which reduces area overhead significantly. The experimental results show that this architecture achieves more thorough fault coverage with minimal impact on the processor performance, while exhibiting reduced latency and area overhead compared with the DCLS-related previous work.