| 基于FPGA的FIR数字滤波器算法实现 |
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| 引用本文： | 蒋垒,王昌林,刘鎏,许冲. 基于FPGA的FIR数字滤波器算法实现[J]. 舰船电子工程, 2006, 26(1): 151-156 |
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| 作者姓名： | 蒋垒 王昌林 刘鎏 许冲 |
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| 作者单位： | 1. 解放军电子工程学院,合肥,230037
2. 解放军68215部队,民和,810800 |
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| 摘 要： | 从分析FIR数字滤波器的原理和设计方法入手，主要针对基于FPGA实现数字滤波器乘法器的算法进行了比较研究，并通过一个8阶FIR低通滤波器的具体设计，简要分析比较了几种算法的优越性和缺点，从而充分发掘和利用FPGA的高速特性。
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| 关 键 词： | VHDL FPGA 数字滤波器 |
| 收稿时间： | 2005-09-07 |
| 修稿时间： | 2005-09-26 |
Design of FIR Filter in FPGA |
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| Jiang Lei,Wang Changlin,Liu Liu,Xu Chong. Design of FIR Filter in FPGA[J]. Ship Electronic Engineering, 2006, 26(1): 151-156 |
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| Authors: | Jiang Lei Wang Changlin Liu Liu Xu Chong |
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| Affiliation: | 1. Hefei PLA Electric Engineering Institute ,Hefei 230037;2. PLA of 68215 ,Minhe 810800 |
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| Abstract: | This paper presentes the theory and design about FIR filter in FPGA. In the article , it designs a 8 stairs lowpass digital filter. Though this example, it discusses some kinds of algorithmic of multiplier in the FIR filter, and contrasted their merits and defects. Then it finds a feasible and efficient method to design the FIR filter. |
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| Keywords: | VHDL FPGA FIR filter |
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