| 嵌入式以太网控制芯片的低功耗DFT设计 |
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| 引用本文： | 邹连英,郑朝霞.嵌入式以太网控制芯片的低功耗DFT设计[J].舰船电子工程,2009,29(5):146-148. |
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| 作者姓名： | 邹连英 郑朝霞 |
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| 作者单位： | 1. 武汉工程大学电气信息学院,武汉,430074
2. 华中科技大学电子科学与技术系,武汉,430074 |
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| 摘 要： | 基于一款嵌入式以太网控制芯片,对不同电路采用不同的低功耗DFT测试技术,以获得较低的测试成本和测试功耗：对于数字逻辑电路,采用了基于扫描链的测试技术,实现了减少翻转次数的测试电路结构;对于片内集成的SRAM、ROM存储器,采用了基于MBIST的测试技术,通过实现准单跳变测试向量生成电路,屏蔽掉无用的测试向量;同时,采用门控时钟等方法来降低CUT输入端的活动性,从而降低CUT上的动态测试功耗;通过采用这些测试方法,该芯片的故障覆盖率可达到97%。
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| 关 键 词： | 可测性设计 自建测试设计 扫描链 |
Low-power DFT Design of Embedded Ethernet Controller |
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| Zou Lianying,Zheng Zhaoxia.Low-power DFT Design of Embedded Ethernet Controller[J].Ship Electronic Engineering,2009,29(5):146-148. |
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| Authors: | Zou Lianying Zheng Zhaoxia |
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| Institution: | Zou Lianying,Zheng Zhaoxia(School of Electric ＆ Information Engineering, Wuhan Institute of Technology , Wuhan 430074) Department of Electronic Science＆Technology, Huazhong University of Science＆Technology, Wuhan 430074) |
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| Abstract: | In this paper, low power DFT of an Ethernet controller is presented. In order to achieve high fault coverage, low test power and low test cost, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic IP; BIST based method is employed for the on-chip SRAM and ROM. For reducing the power consumptions, gated clock scheme is implemented, and the non-detecting vectors are filtered by quasi single-jump signal generation circuits. By all means above, the result shows that the fault coverage may reach 97%. |
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| Keywords: | design for test built in self test scan chain |
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