| 基于FPGA/CPLD的高速和低速UART的设计及其应用 |
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| 引用本文： | 王永州,范多旺.基于FPGA/CPLD的高速和低速UART的设计及其应用[J].铁路计算机应用,2006,15(10):1-4. |
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| 作者姓名： | 王永州 范多旺 |
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| 作者单位： | 兰州交通大学,光电技术与智能控制教育部重点实验室,兰州,730070 |
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| 摘 要： | 利用计算机软件技术(EDA技术)和FPGA/CPLD的灵活性可以方便快速地设计高速和低速的UART.高速的UART可以用在光纤通信上,低速的UART可以用在FPGA/CPLD和单片机的通信上.设计中包含UART的发送模块、接收模块和波特率发生器,所有功能的实现全部采用VHDL硬件描述语言来进行描述.设计、综合、仿真在QUARTUS Ⅱ软件开发环境下实现.
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| 关 键 词： | UART VHDL FPGA/CPLD 设计 |
| 文章编号： | 1005-8451(2006)10-0001-04 |
| 收稿时间： | 2006-05-10 |
| 修稿时间： | 2006年5月10日 |
Design and application of high speed and low speed UART based on FPGA/CPLD |
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| WANG Yong-zhou,FAN Duo-wang.Design and application of high speed and low speed UART based on FPGA/CPLD[J].Railway Computer Application,2006,15(10):1-4. |
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| Authors: | WANG Yong-zhou FAN Duo-wang |
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| Institution: | Automatic Control Research Institute, Key Laboratory of Opto-Eleetronic Technology and Intelligent Control Ministry of Education, Lanzhou. Jiaotong University, Lanzhou 730070, China |
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| Abstract: | Using EDA and the agility of FPGA/CPLD could easily and quickly design the high speed and low speed UART. High speed UART could be used on the optical fibre communication and low speed UART could be used on the communication of FPGA/CPLD with SCM.This design included the transmitter module, the receiver module and the Baudrate Generator. All function were described by VHDL. The implementation of design, simulation and synthesis were completed by the development software of QUARTUS II. |
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| Keywords: | UART VHDL FPGA/CPLD |
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