基于分布式算法FIR滤波器的FPGA实现

在利用FPGA实现数字信号处理方面,分布式算法发挥着关键作用,与传统的乘积-积结构相比,具有并行处理的高效性特点.研究了基于FPGA利用分布式算法来并行实现FIR数字滤波器硬件电路的方法.首先介绍了FIR数字滤波器的基本概念和分布式算法的基本原理,然后讨论了具体的硬件实现电路,FIR数字滤波器用VHDL进行描述并综合到FPGA中,仿真结果表明,该结构完全可以达到实际应用的要求.介绍的分布式算法数字FIR滤波器FPGA并行实现的方法可使滤波器的设计简单化,利用加法器代替乘法器不仅节约了硬件资源,而且提高了数字信号处理的速度.

DA- Based FIR Realization in FPGA

Distributed arithmetic takes the key role in digital signal process realization in FPGAs. Compared with the traditional multiply- structure, it has the feature of efficient parallel process. In this paper, we discuss the DA- Based FIR realization in FPGA. We recommend basal concept of the FIR filter and the theory of the distributed arithmetic firstly, then discuss the hardware circuit realization in FPGA. The FIR filter is depicted by VHDL and synthesized to FPGA, the result of simulations proves that this method is feasible and efficient. It can make the design easier. It not only save the resource of hardware, but also raise the speed of digital signal process by using adder substitute multiplier.