| IEC61850-9-2标准下合并单元的研制 |
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| 引用本文： | 田丽平. IEC61850-9-2标准下合并单元的研制[J]. 华东交通大学学报, 2012, 29(3): 36-39 |
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| 作者姓名： | 田丽平 |
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| 作者单位： | 华东交通大学电气与电子工程学院,江西南昌,330013 |
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| 摘 要： | 针对当前合并单元的研究现状,分析了合并单元的采样值映射模型IEC61850-9-2及其实现方法,在此基础上设计了一种基于现场可编程门阵列(FPGA)的合并单元装置。该装置通过在FPGA芯片上配置NiosII软核处理器和相关接口,完成合并单元同步、多路数据接收和处理以及以太网通信等功能,能满足电子式互感器数字接口的要求。
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| 关 键 词： | IEC61850-9-2 合并单元 FPGA |
A Research on Merging Unit Based on IEC61850-9-2 |
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| Tian Liping. A Research on Merging Unit Based on IEC61850-9-2[J]. Journal of East China Jiaotong University, 2012, 29(3): 36-39 |
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| Authors: | Tian Liping |
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| Affiliation: | Tian Liping(School of Electrical and Electronic Engineering,East China Jiaotong University,Nanchang 330013,China) |
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| Abstract: | Aiming at the current research situation of the merging unit,the value of the merging sampling unit mapping model IEC61850-9-2 and its implementation are analyzed.A merging unit based on FPGA is designed.This device realizes the functions of merging unit synchronization,multi-channels acquisition,and Ethernet communication by configuring NiosII soft core CPU and some modules on a PFGA.This method can fulfill the requirements of reliability for electronic transducer. |
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| Keywords: | IEC61850-9-2 merging unit FPGA |
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