| 单片机与FPGA的总线接口的设计与实现 |
| |
| 引用本文： | 刘余才,王晓明,葛立明.单片机与FPGA的总线接口的设计与实现[J].兰州铁道学院学报,2009,28(1):79-81. |
| |
| 作者姓名： | 刘余才 王晓明 葛立明 |
| |
| 作者单位： | 兰州交通大学光电技术与智能控制教育部重点实验室,甘肃,兰州,730070
|
| |
| 摘 要： | 介绍了AVR单片机与FPGA的总线接口的设计与实现，采用ATmega128微控制器与Ahera公司的Cyclone系列芯片EP1C6Q24017进行硬件设计，详细阐述了硬件电路的结构，给出了基于硬件描述语言Verilog HDL的接口的设计及其仿真波形．总线接口的设计是为了解决串行数据传输速度慢的问题，方法采用FPGA来实现并行数据的传输．最后结果是设计的Verilog程序符合并行数据传输的要求，并验证了并行数据传输模式远远优越于传统的串行传输模式．
|
| 关 键 词： | 单片机 FPGA 总线接口 Verilog |
Design and Implementation of the Bus Interface of MCU and FPGA |
| |
| LIU Yu-cai,WANG Xiao-ming,GE Li-ming.Design and Implementation of the Bus Interface of MCU and FPGA[J].Journal of Lanzhou Railway University,2009,28(1):79-81. |
| |
| Authors: | LIU Yu-cai WANG Xiao-ming GE Li-ming |
| |
| Institution: | (Key Laboratory of Optcreleetronie Technology and Intelligent Control(Ministry of Education), Lanzhou Jiaotong University, Lanzhou 730070, China) |
| |
| Abstract: | The design and implementation of AVR MCU and FPGA bus interface are introduced,using ATmega128 microcontroller and Altera's Cyclone serial chip EP1C6Q240I7 for hardware design.The structure of hardware circuit is elaborated in detail and the interface design and its simulation waveforms are presented using the hardware language of Verilog HDL.In order to solve the problem of the slow transmission speed of the serial data,we need design the bus interface.The method of the design is that we can use FPGA to re... |
| |
| Keywords: | verilog |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
