| 基于NIOS II处理器GPS/GSM车辆监控系统终端设计 |
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| 引用本文： | 王永州,范多旺,金静,桑兴民.基于NIOS II处理器GPS/GSM车辆监控系统终端设计[J].铁路计算机应用,2007(2). |
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| 作者姓名： | 王永州 范多旺 金静 桑兴民 |
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| 作者单位： | 兰州交通大学光电技术与智能控制教育部重点实验室 兰州730070 |
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| 摘 要： | 利用SOPC Builder可以在很短的时间内把NIOS II CPU、Avalon总线、外围设备和存储器接口、片内调试模块等集成在一起生成系统需要的NIOS II处理器,然后用Quartus II设计软件把NIOS II处理器和GPS接口、GSM接口及其它外部设备接口结合在一起编译下载到FPGA芯片中即完成系统的硬件设计;软件设计通常采用C/C 语言编写并用NIOS II IDE编译下载到FPGA中。
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| 关 键 词： | NIOS II FPGA GPS GSM |
Design of GPS/GSM vehicle monitoring system terminal based on NIOS II processor |
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| WANG Yong-zhou,FAN Duo-wang,JIN Jing,SANG Xing-min.Design of GPS/GSM vehicle monitoring system terminal based on NIOS II processor[J].Railway Computer Application,2007(2). |
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| Authors: | WANG Yong-zhou FAN Duo-wang JIN Jing SANG Xing-min |
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| Abstract: | It was taken very short time to integrate NIOS II CPU, the Avalon address lines, the interfaces of peripherals and memories and the inner debug module into the requisite NIOS II processor using the SOPC Builder. Then it needed to use the Quartus II design software to combine NIOS II processor with GPS interface, GSM interface and other peripheral interfaces, finishing the hardware design by compiling and downloading it into the FPGA chip. The software was usually writed with C or C language and to be compiled and downloaded into FPGA by NIOS II IDE. |
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| Keywords: | NIOS II Field-Programmable Gate Array GPS GSM |
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