| 一种快速除法算法的FPGA实现 |
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| 引用本文： | 王一帮,李芳,严奉轩,吴霆.一种快速除法算法的FPGA实现[J].舰船防化,2011(1). |
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| 作者姓名： | 王一帮 李芳 严奉轩 吴霆 |
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| 作者单位： | 中国船舶重工集团公司第七一八研究所; |
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| 摘 要： | 介绍了一种新的除法算法,该算法是利用Taylor公式,用两次乘法操作和一张较小的查找表实现。整个算法采用verilog语言描述,设计灵活、实现简单。仿真效果表明该算法具备较高的精度与较快的运算速度。
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| 关 键 词： | 除法 FPGA Verilog 查表法 |
Implementation of a Fast Division Algorithm on FPGA |
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| Wang Yi-bang,Li Fang,Yan Feng-xuan,Wu Ting.Implementation of a Fast Division Algorithm on FPGA[J].Chemical Defence on Ships,2011(1). |
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| Authors: | Wang Yi-bang Li Fang Yan Feng-xuan Wu Ting |
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| Institution: | Wang Yi-bang,Li Fang,Yan Feng-xuan,Wu Ting (The 718th Research Institute of CSIC,Handan 056027,China) |
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| Abstract: | A novel division algorithm is introduced by the use of Taylor formula, which uses two multiplication operations and a small look-up table. The algorithm is described by verilog language, and it is flexible and simple. Simulation result shows that the algorithm has high accuracy and fast processing speed. |
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| Keywords: | Division FPGA Verilog Look-up table |
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