| 基于DSP和FPGA的高速串行通信系统设计 |
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| 引用本文： | 张雪,徐晓苏,张国龙.基于DSP和FPGA的高速串行通信系统设计[J].舰船电子工程,2009,29(5):66-69. |
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| 作者姓名： | 张雪 徐晓苏 张国龙 |
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| 作者单位： | 东南大学仪器科学与工程学院,南京,210096 |
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| 基金项目： | 国家自然科学基金，总装备部预研项目，原国防科工委基础科研项目，教育部高等学校博士学科点专项科研基金 |
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| 摘 要： | 在基于DSP和FPGA的嵌入式组合导航系统中,为了满足系统微型化、高性能度的要求,采用DSP作为处理器,由PFGA集成多串行口的扩展等其他功能。DSP通过外部存储器接口（EMIF）接口实现和FPGA通信。利用DSP的EDMA功能完成FPGA内部FIFO和DSP内部RAM中乒乓缓冲器之间的数据传输,可以使DSP专注于复杂的导航解算,从而可提高系统串行通信的效率和速度。
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| 关 键 词： | DSP FPGA UART FIFO EDMA |
Design of High Speed Serial Communication Based on DSP and FPGA |
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| Zhang Xue,Xu Xiaosu,Zhang Guolong.Design of High Speed Serial Communication Based on DSP and FPGA[J].Ship Electronic Engineering,2009,29(5):66-69. |
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| Authors: | Zhang Xue Xu Xiaosu Zhang Guolong |
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| Institution: | (School of Instrument Science and Engineering, Southeast University, Nanjing 210096) |
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| Abstract: | In the embedded integrated navigation system based on DSP and FPGA, to meet it＇s micromation and high performance, DSP is used to be a processor and FPGA performs expanding multi UART and other functions. DSP interfaces to FPGA by DSP＇s EMIF. In addition, EDMA was used to transmit the data between the FPGA FIFOs and ping-pong buffers designed in the RAM of DSP. In this way, DSP can be devoted in complicated navigation algorithm and enhance the efficiency and speed of the serial communication. |
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| Keywords: | DSP FPGA UART FIFD EDMA |
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