A high-performance low cost inverse integer transform architecture for AVS video standard

A high-performance, low cost inverse integer transform architecture for advanced video standard (AVS) video coding standard was presented. An 8×8 inverse integer transform is required in AVS video system which is compute-intensive. A hardware transform is inevitable to compute the transform for the real-time ap-plication. Compared with the 4×4 transform for H.264/AVC, the 8×8 integer transform is much more complex and the coefficient in the inverse transform matrix Ts is not inerratic as that in H.264/AVC. Dividing the Ts into matrix S8 and R8, the proposed architecture is implemented with the adders and the specific CSA-trees instead of multipliers, which are area and time consuming. The architecture obtains the data processing rate up to 8 pixels per-cycle at a low cost of area. Synthesized to TSMC 0.18 μm COMS process, the architecture attains the operating frequency of 300 MHz at cost of 34 252 gates with a 2-stage pipeline scheme. A reusable scheme is also introduced for the area optimization, which results in the operating frequency of 143 MHz at cost of only 19 758 gates.     

Design and Implementation of the Motion Compensation Module for HDTV Video Decoder

Introduction The HDTV format adopts MPEG-2MP@HLvideo standard for the encoding and decoding ofhigh definition video information[1].Motion com-pensation is one of the key techniques used to con-siderably decrease the time redundancy of a videosequence and make the format reach a high com-pression ratio.As for hardware implementation,however,the motion compensation module is one ofthe most computation-intensive and I/O intensiveparts in an HDTV video decoder[2],and thereforeit is also the…     

A High-performance Low Cost Inverse Integer Transform Architecture for AVS Video Standard

A high-performance, low cost inverse integer transform architecture for advanced video standard (AVS) video coding standard was presented. An 8×8 inverse integer transform is required in AVS video system which is compute-intensive. A hardware transform is inevitable to compute the transform for the real-time ap-plication. Compared with the 4×4 transform for H.264/AVC, the 8×8 integer transform is much more complex and the coefficient in the inverse transform matrix Ts is not inerratic as that in H.264/AVC. Dividing the Ts into matrix S8 and R8, the proposed architecture is implemented with the adders and the specific CSA-trees instead of multipliers, which are area and time consuming. The architecture obtains the data processing rate up to 8 pixels per-cycle at a low cost of area. Synthesized to TSMC 0.18 μm COMS process, the architecture attains the operating frequency of 300 MHz at cost of 34 252 gates with a 2-stage pipeline scheme. A reusable scheme is also introduced for the area optimization, which results in the operating frequency of 143 MHz at cost of only 19 758 gates.     

面向Pointer色域的优化色差系统设计

为研究宽色域视频信号与现行电视系统的兼容传输,以Pointer色域为宽色域HDTV传输系统的目标色域,基于最小外接矩形（MER）技术,提出了RC和SC两种优化算法,得到了与ITU-RBT.709常规HDTV系统兼容传输的优化色差信号,并基于此建立新的色差编码系统.该系统在不改变现行HDTV传输系统基色和基准白色度参数、不扩大亮度和色差传输信号动态范围前提下,将可传输的Pointer色域由44%提高到100%,实现了宽色域HDTV信号的兼容传输.文中计算了信号收端重显色差,结果表明,与宽色域ITU-RBT.1361系统相比,优化的色差信号系统色视觉保真度较高.     

地铁PIS系统中的视频技术

本文综合国内多个地铁PIS项目，根据PIS系统业务需求，并结合计算机视频处理技术、高清电视技术、视频编码及传输技术的发展及应用，对PIS的发展进行了探讨。