| FPGA设计中跨时钟域同步方法的研究 |
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| 引用本文： | 唐辉艳,李绍胜.FPGA设计中跨时钟域同步方法的研究[J].铁路计算机应用,2011,20(5):43-44,47. |
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| 作者姓名： | 唐辉艳 李绍胜 |
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| 作者单位： | 北京邮电大学,信息与通信工程学院,北京100876%中国软件与技术服务有限公司,北京,100080 |
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| 基金项目： | 北京市军工研究发展计划项目 |
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| 摘 要： | 跨时钟域的同步问题是现场可编程门阵列(FPGA)设计中的一个难点,本文分析跨时钟域所带来的亚稳态,提出FPGA设计中跨时钟域的同步方法,重点介绍利用异步FIFO实现跨时钟域的同步方法,并用Verilog HDL硬件描述语言设计该方案,验证该方法的正确性.
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| 关 键 词： | FPGA 跨时钟域 同步 亚稳态 |
| 收稿时间： | 2011-05-15 |
Research on synchronization of asynchronous clock in FPGA design |
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| TANG Hui-yan,LI Shao-sheng.Research on synchronization of asynchronous clock in FPGA design[J].Railway Computer Application,2011,20(5):43-44,47. |
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| Authors: | TANG Hui-yan LI Shao-sheng |
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| Institution: | TANG Hui-yan1,LI Shao-sheng2(1.School of Information and Telecommuncation Engineering,Beijing University of Post and Telecommunications,Beijing 100876,China,2.China National Software & Service CO.LTD,Beijing 100080,China) |
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| Abstract: | It was a difficult problem to synchronous of asynchronous clock in FPGA design.This paper introduced the metastable state phenomena and the relative problems.Several approaches of synchronization to deal with the problem were discussed.It was introduced especially the approach that used FIFO to implement the synchronize of asynchronous clock in FPGA design,simulated and verified the approach with Verilog HDL,proved its feasibility. |
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| Keywords: | FPGA |
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