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Low-power and Low-cost Design of Survival Memory Unit for 1000Base-T Gigabit Ethernet Transceiver
作者姓名:诸悦  戎蒙恬
作者单位:System and Chip Research Center Shanghai Jiaotong Univ.,System and Chip Research Center Shanghai Jiaotong Univ.,Shanghai 200240 China,Shanghai 200240 China
基金项目:National Science Fund for Creative ResearchGroups (No.60521002),Shanghai NaturalScience Foundation(No.037062022)
摘    要:Introduction The Gigabit Ethernet (GbE) on category-5unshielded twins pair (UTP) which corresponds tothe IEEE 802.3 ab1000 Base-T standard has grad-ually become the main trend of local area network(LAN). To take advantage of the additional cod-ing gain offered by the trellis-coded modulation(TCM) coding without using a maximum likeli-hood sequence estimation (MLSE) decoder, a deci-sion feedback sequence estimate1](DFSE) decodercan be used2-6]. Like the decision feedback equalizer …


Low-power and Low-cost Design of Survival Memory Unit for 1000Base-T Gigabit Ethernet Transceiver
ZHU Yue,RONG Meng-tian.Low-power and Low-cost Design of Survival Memory Unit for 1000Base-T Gigabit Ethernet Transceiver[J].Journal of Shanghai Jiaotong university,2006,11(4).
Authors:ZHU Yue  RONG Meng-tian
Institution:System and Chip Research Center,Shanghai Jiaotong Univ.,Shanghai 200240,China
Abstract:Types of hybrid architectures survivor memory unit (SMU) is presented,which are applicable to IEEE 802.3 ab 1000 Base-T Gigabit Ethernet (GbE) transceiver. Area, power and decoder latency were taken into account and most efficient architectures were compared to optimize area/power tradeoff in different kinds of applications. Suitable SMU architectures are given out respectively in area-restrict, power-restrict and latency-restrict designs. A power-efficient architecture was selected in our GbE project. It provides 48% improvement in area and 71% amelioration in power, compared to classical register exchange architecture (REA) SMU.
Keywords:Gigabit Ethernet decision feedback sequence estimate survival memory unit register exchanger architecture trace back architecture
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