A high-performance low cost inverse integer transform architecture for AVS video standard |
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Authors: | Yu-fei Li Qin Wang Yu-zhuo Fu |
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Institution: | (1) Department of Computer Science and Engineering, Shanghai Jiaotong University, Shanghai, 200240, China;(2) School of Micro-electronics, Shanghai Jiaotong University, Shanghai, 200240, China |
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Abstract: | A high-performance, low cost inverse integer transform architecture for advanced video standard (AVS) video coding standard
was presented. An 8 × 8 inverse integer transform is required in AVS video system which is compute-intensive. A hardware transform
is inevitable to compute the transform for the real-time application. Compared with the 4 × 4 transform for H.264/AVC, the
8 × 8 integer transform is much more complex and the coefficient in the inverse transform matrix T
8 is not inerratic as that in H.264/AVC. Dividing the T
8 into matrix S
8 and R
8, the proposed architecture is implemented with the adders and the specific CSA-trees instead of multipliers, which are area
and time consuming. The architecture obtains the data processing rate up to 8 pixels per-cycle at a low cost of area. Synthesized
to TSMC 0.18 μm COMS process, the architecture attains the operating frequency of 300 MHz at cost of 34 252 gates with a 2-stage
pipeline scheme. A reusable scheme is also introduced for the area optimization, which results in the operating frequency
of 143 MHz at cost of only 19 758 gates.
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Keywords: | inverse integer transform high-definitioin television (HDTV) carry-save adder (CSA) tree pipeline advanced video standard (AVS) |
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