| 并行分布式运算FIR滤波器的FPGA实现 |
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| 引用本文： | 王旭东,周安栋,周冬成.并行分布式运算FIR滤波器的FPGA实现[J].舰船电子工程,2005,25(5):64-66. |
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| 作者姓名： | 王旭东 周安栋 周冬成 |
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| 作者单位： | 海军工程大学,武汉430033 |
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| 摘 要： | 研究了2比特并行分布式计算（2-bit PDA）在FPGA中实现了FIR滤波器的应用,并在Altera公司的APEX20K1500E系列FPGA中实现了48阶FIR滤波器,实际结果表明使用该方法实现滤波器不但节省了逻辑单元,而且和普通的并行分布式方法相比还提高了运算速率,从而使该滤波器用于实时信号处理时有更大的优越性.
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| 关 键 词： | 分布式算法 有限冲激响应（FIR）滤波器 现场可编程逻辑阵列 |
| 收稿时间： | 2005-05-08 |
| 修稿时间： | 2005-05-17 |
Realization of Parallel- distributed Arithmetic Method FIR Filter Based on FPGA |
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| Wang Xudong, Zhou Andong, Zhou Dongcheng.Realization of Parallel- distributed Arithmetic Method FIR Filter Based on FPGA[J].Ship Electronic Engineering,2005,25(5):64-66. |
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| Authors: | Wang Xudong Zhou Andong Zhou Dongcheng |
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| Institution: | Naval University of Engineering,Wuhan 430033 |
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| Abstract: | We address the FIR filter based on 2 bits parallel-distributed arithmetic method(2-bit PDA) in FPGA in this paper,and the realization of 48-order FIR filter with FPGA Altera Apex20K1500E.The practical result deconstrate that the way of realizing filter based on this method reduces the number of logic cell,but also as comparing with the common distributed arithmetic method,increases the calculation speed,consequently have great advantage in applying the filter in real-time signal processing. |
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| Keywords: | DA FIR filter FPGA |
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