Optimization of CMOS repeater driven interconnect RC line using genetic algorithm

In this work, optimization of complementary metal oxide semiconductor (CMOS) repeater driven interconnect resistive-capacitive (RC) line is carried out using genetic algorithm (GA). This work is aimed at powerdelay- product (PDP) minimization of RC interconnect at 180 nm technology node. The algorithm simultaneously optimizes the values of supply voltage, number of repeaters and repeater width for delay and PDP minimization. The accuracy of results obtained is verified by simulations from Cadence virtuoso tool. For delay minimization, comparison of GA results with previous results of the literature shows an improvement of 44.4% in the value of the optimal number of repeaters required. This improvement is obtained by increasing the repeater size, which also increases power dissipation, so a tradeoff has also been achieved in terms of PDP minimization. The comparison of PDP results obtained in this work, with the results at 70, 100, and 130 nm technologies from literature shows improvement in optimal number of repeaters required. The results of algorithm and simulations are in good agreement and demonstrate the validity of proposed algorithm.