对采样保持电路中电容失配的误差分析与仿真

对于模数转换器（ADC），电容失配所产生的误差是一种主要的非线性误差源．分析了采样保持电路的工作原理和由电容失配产生的误差，并利用有源误差平均技术对文中采样保持电路进行误差平均．在采样频率为100MHz情况下，输入偏移量为0．75V，振幅为0．375V，频率为2．5MHz的正弦差分信号，经误差平均电路后电容失配造成的误差由1．1mV降至0．8μV，证明了有源电容失配校准方法的有效性．

Simulation and Analysis of Capacitor Mismatch Error in Sample and Hold Circuit

To reduce analog to digital convertion non-linear error, the sample-and-hold circuit working principle and the error caused by the capacitor mismatches are analyzed, and the active capacitor error averaging （ACEA） technique is applied to calibrate the capacitor mismatch error. In the sampling frequency of 1130 MHz,a pair of sinusoidal differential signals is input with the input offset of 0.75 V, with an amplitude of ± 0.375 V at a frequency of 2.5 MHz, the mismatch errors is decreased to 0.8μV from 1.1 mV after active capacitor error averaging, which proves the active capacitor mismatch calibration method is effective.