| 基于VHDL的有限状态机电路设计 |
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| 引用本文： | 林若波. 基于VHDL的有限状态机电路设计[J]. 中国水运, 2007, 5(9): 210-212 |
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| 作者姓名： | 林若波 |
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| 作者单位： | 揭阳职业技术学院机电系 |
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| 摘 要： | 有限状态机(FSM)及其应用技术是数字系统设计中的重要组成部分,基于VHDL的有限状态机设计已经成为EDA技术中的主要设计方法。论文通过对AD采样控制状态机的原理分析,介绍了基于VHDL平台的有限状态机的设计技术和实现过程。
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| 关 键 词： | 有限状态机(FSM) VHDL EDA |
| 文章编号： | 1006-7973(2007)09-0210-03 |
| 修稿时间： | 2007-07-09 |
Based on VHDL limited state machine circuit design |
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| Lin Ruobo. Based on VHDL limited state machine circuit design[J]. China Water Transport, 2007, 5(9): 210-212 |
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| Authors: | Lin Ruobo |
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| Abstract: | Finite State Machine (FSM) and its application technology is an important constituent in the digital system design, which it has became the main design method in the EDA technology based on the VHDL design. With the theory analysis of AD sampling control Finite State Machine, The paper introduces the design technology and the realization process of FSM based on the VHDL. |
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