| 一种用于FPGA流水线设计的时钟技术 |
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| 引用本文： | 周冬成,王永斌. 一种用于FPGA流水线设计的时钟技术[J]. 舰船电子工程, 2005, 25(6): 91-94 |
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| 作者姓名： | 周冬成 王永斌 |
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| 作者单位： | 海军工程大学电子工程学院,武汉,430033 |
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| 摘 要： | 介绍了一种时钟流水线技术——单脉冲流水线（PP-流水线），它可用于在FPGA中实现异步流水线操作。加入数据完成电路，利用可变的数据处理时间，这种技术亦可用于同步流水线设计。PP-流水线还可以降低流水线电路的时钟树功耗。这些应用可通过FPGA电路的综合后模拟得到验证。
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| 关 键 词： | 流水线 FPGA 时钟 |
| 收稿时间： | 2005-05-27 |
| 修稿时间： | 2005-06-09 |
A Clocking Technique Used in FPGA Pipelined Designs |
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| Zhou Dongchen,Wang Yongbin. A Clocking Technique Used in FPGA Pipelined Designs[J]. Ship Electronic Engineering, 2005, 25(6): 91-94 |
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| Authors: | Zhou Dongchen Wang Yongbin |
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| Affiliation: | Naval University of Engineering,Wuhan 430033 |
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| Abstract: | This paper presents a clocking pipeline technique referred to as a single-pulse pipeline(PP-Pipeline).It can be applied to the operation of asynchronous micropipeline in FPGA devices.The technique can be extended to include data-completion circuity to take advantage of variable data-completion processing time in synchronous pipelined designs.It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits.These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. |
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| Keywords: | pipeline FPGA clock |
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