Parallel-pipelined architecture of H.264 deblocking filter with adaptive dynamic power |
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Authors: | Hu Wei Tao Lin |
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Affiliation: | WEI Hu1,LIN Tao2 (1. Department of Electronic Engineering,Shanghai Jiaotong University,Shanghai 200240,China,2. Institute of Very Large Scale Integrated Circuits,Tongji University,Shanghai 200331,China) |
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Abstract: | In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be ... |
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Keywords: | deblocking filter adaptive dynamic power parallel processing pipeline H.264 |
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