| Xilinx DDR2 IP核控制器设计 |
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| 引用本文： | 邹连英,余峰.Xilinx DDR2 IP核控制器设计[J].舰船电子工程,2012,32(6):139-142. |
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| 作者姓名： | 邹连英 余峰 |
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| 作者单位： | 武汉工程大学电气信息学院,武汉,430205 |
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| 摘 要： | 提出一种便于用户操作并能快速运用到产品的DDR2控制器IP核的FPGA实现，使用户不需要了解DDR2的原理和操作方式的情况下，依然可以通过IP核控制DDR2。简单介绍了DDR2的特点和操作原理，并对DDR2控制器的IP核进行了模块化的划分，分析了每个模块的功能。强调了用户接口功能的完善，并介绍了IP核的操作流程，使每个用户都能轻松的使用该IP核。
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| 关 键 词： | DDR2 控制器 IP核 FPGA |
Design of Xilinx DDR2 IP Controller |
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| ZOU Lianying,YU Feng.Design of Xilinx DDR2 IP Controller[J].Ship Electronic Engineering,2012,32(6):139-142. |
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| Authors: | ZOU Lianying YU Feng |
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| Institution: | (School of Electrical and Information Engineering,Wuhan Institute of Technology,Wuhan 430205) |
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| Abstract: | This paper presents a DDR2 Controller IP core of FPGA implementation which user-friendly and quickly applied to the product.The IP core allows the user does not need to understand the principles and practices DDR2 circumstances,and can still control the DDR2.This thesis briefly introduces that the characteristics and operating principles of DDR2,and analyze that the function of each module in the DDR2 controller IP core.Emphasized the function of the perfect user interface,described the IP core operational processes in the paper,so that each user can easily use the IP core. |
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| Keywords: | DDR2 controller IP core FPGA |
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