| RS编译码的FPGA实现 |
| |
| 引用本文： | 丁忠义,袁国材.RS编译码的FPGA实现[J].舰船电子工程,2008,28(11). |
| |
| 作者姓名： | 丁忠义 袁国材 |
| |
| 作者单位： | 中国船舶重工集团公司第722研究所,武汉,430079 |
| |
| 摘 要： | RS码作为一类强大和被广泛使用的前向纠错码,被广泛应用于数字系统的信道编码方案中.介绍RS码的编码原理和时域迭代泽码算法,在此基础上用Verilog HDL设计实现出RS码编码器和译码器.
|
| 关 键 词： | RS码 FPGA实现 |
Implementation of RS Coder and Decoder Using FPGA |
| |
| Ding Zhongyi,Yuan Guocai.Implementation of RS Coder and Decoder Using FPGA[J].Ship Electronic Engineering,2008,28(11). |
| |
| Authors: | Ding Zhongyi Yuan Guocai |
| |
| Institution: | Ding Zhongyi Yuan Guocai (No.722 Research & Development Institute of CSIC,Wuhan 430079) |
| |
| Abstract: | Reed-Solomon(RS)code is one of the most powerful and widely used coding schemes for FEC.RS code were used in the digital channel coding scheme.In this thesis,the code theory and time-domain iterative decode algorithm of RS code is introduced,RS coder and decoder are designed and implemented in this base with the Verilog HDL. |
| |
| Keywords: | Verilog HDL |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
