CMOS集成电路功耗分析及其优化方法

电子产品功耗的大小不仅限制了便携设备电池使用时间，也在一定程度上影响着设备性能。研究降低功耗的电路设计技术意义重大。CMOS集成电路功耗的物理来源主要有两种：由于CMOS管工作状态变化而引起的动态功耗和由于漏电流而产生的静态功耗。针对决定功耗大小的具体因素，从制造工艺和具体设计角度，讨论了几种降低CMOS集成电路功耗技术。

Power Analysis and Optimization Techniques for CMOS Integrated Circuits

The electronic products' power dissipation not only limits the using time of portable equipments,but also affects the capability of circuits on a certain extent.It is important to research the designing technology of reducing the power dissipation of circuits.It has two main source of power dissipation for CMOS integrated circuits:the dynamic power dissipation,which is caused by the change of CMOS transistor working state,and the static power dissipation,which is caused by the leaking current.Focusing on the causing factors of power dissipation,several techniques of low-power design have been discussed in this paper.