| 利用冗余态参与状态分配设计时序逻辑电路 |
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| 引用本文： | 王淑芝,梁海峰.利用冗余态参与状态分配设计时序逻辑电路[J].大连铁道学院学报,2002,23(1):48-50,58. |
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| 作者姓名： | 王淑芝 梁海峰 |
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| 作者单位： | 大连铁道学院电气信息分院，辽宁大连116028 |
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| 摘 要： | 在时序逻辑电路的设计中，利用电路所存原冗余来参与状态分配，更符合“A－H规则”，从而获得较简单的电路结构，并且消除了无效状态和所谓的自校正问题，是值得推广应用的一种新的状态分配技术。
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| 关 键 词： | 设计 时序逻辑电路 冗余态 状态分配 A－H规则 自校正 |
Design of Sequential Logic Circuit by Redudent State Assignment |
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| WANG Shu-zhi,LIANG Hai-feng.Design of Sequential Logic Circuit by Redudent State Assignment[J].Journal of Dalian Railway Institute,2002,23(1):48-50,58. |
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| Authors: | WANG Shu-zhi LIANG Hai-feng |
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| Abstract: | In the design of the sequential logic circuit, redundant state is used to assign the state, so the assignment is more consistent to the A -H rule, and simple sequential structure can be obtained. The invalid state and the so - called sell' - correcting problem also are overcome. The new technique of the state assignment can be used extensively. |
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| Keywords: | redundant state state assignment A - H rule self - correcting |
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