一种CMOS静态D锁存器的版图设计

集成电路版图设计是实现集成电路制造所必不可少的设计环节,本文在正确理解MOS场效应晶体管的物理特性、工作原理以及CMOS逻辑电路结构基础之上,逐级优化实现了由传输门构成的CMOS D锁存器的逻辑电路和晶体管级电路.然后根据CMOS工艺规则,利用Tanner Tool软件进行了CMOS 2μm N阱的D锁存器的版图设计.通过LVS功能验证及延迟时间分析,表明所设计的CMOS D锁存器版图功能正确、性能好、时延小、速度快.

Design of CMOS Static D Latch Layout

Integrated circuit layout design is essential to integrated circuits manufacturing. The design for CMOS D latch layout based on the rules of CMOS technology is realized by Tanner Tool software in this paper. On the basis of the correct understanding of MOSFET physical characteristics, principle and the CMOS logic circuit,the logical circuit and transistor level circuit of D latch were established. According to layout designing rules and the requirements of CMOS process on the layout,a layout corresponding to above transistor circuit is performed. LVS is adopted to compare the functions of the designed layout with the circuit. The simulation results verify that not only the action of D latch layout with CMOS 2μm N-well process is right but also its delaying time is much shorter. So the performance of the designed D latch has good performance.