Uplink Power Saving Potential of Cellular System with Fixed Relays

This paper presented a scheme of relayed cellular mobile telecommunication network, which only employs fixed digital relays and not more than two-hop relay routes. Power saving potential of the network is deeply studied under the assumption of not occupying additional frequency bands （i. e. relays share the same frequency bands as used by the base stations）. Theoretical analysis and simulation results have both shown that, with the same radio coverage requirement, the necessary effective transmission powers in such a relayed network have greatly decreased compared to conventional cellular network.     

OPTIMAL PUNCTURING OF TURBO CODES BASED ON ADS CRITERION

IntroductionTurbo codes[1] has been shown to yield re-markable coding gains close to theoretical limits,yetadmitting a relatively simple iterative decordingtechnique,which are attracting the attention ofmany researchers.Owing to the parallel concate-nation,the code rate ofturbo codes,denoted as R,is low.Puncturing is the predominant strategy toconstruct high code rate turbo codes[2 ,3 ] .Punctur-ing schemes are crucial to the performance ofpunc-tured turbo codes( PTC) .Since any puncturingsc…     

Resource Partitioning and Routing Optimization in Relay Enhanced Cellular Network

A joint routing and resource partitioning scheme were proposed to improve cell capacity and user throughput of cellular network enhanced with two-hop fixed relay nodes (FRNs). Radio resources are partitioned under a reuse partitioning based framework, which guarantees effective and efficient inter-cell interference management. At the same time, each mobile terminal was assigned a channel-dependent route by the routing controller, which tries to maximize the cell capacity under the constraint imposed by reuse partitioning. Intensive computer simulations demonstrate the performance superiority of the FRN enhanced cellular network employing this scheme in comparison with conventional network, as well as the validity of the channel-dependent routing mechanism.     

Interference and Spectral Cellular Network with Efficiency Analysis in Two-hop Fixed Relays in FDD Mode

This paper presented ascheme of two-hop cellular network with fixed relay nodes （FRN）. Based on this scheme, co-channel interference and signal interference ratio（SIR） received by base station（BS） and FRN were analyzed. Both the theoretical analysis and simulation results show that the SIR can be improved significantly when relays are employed in the network. The higher spectral efficiency can be obtained due to the improved two-hop link quality through the use of adaptive modulation and coding （AMC）. The antenna height of FRN and the cell radius of BS and that of FRN influence SIR received by BS and FRN and the system spectral efficiency greatly. The proper antenna height of FRN and cell radius of BS and that of FRN were also given to get the highest spectral efficiency.     

The RSA Cryptoprocessor Hardware Implementation Based on Modified Montgomery Algorithm

RSA (Rivest-Shamir-Adleman)public-key cryptosystem is widely used in the information security area such as encryption and digital signature. Based on the modified Montgomery modular multiplication algorithm, a new architecture using CSA(carry save adder)was presented to implement modular multiplication. Compared with the popular modular multiplication algorithms using two CSA, the presented algorithm uses only one CSA, so it can improve the time efficiency of RSA eryptoproeessor and save about half of hardware resources for modular multiplication. With the increase of encryption data size n, the clock cycles for the encryption procedure reduce in T(n^2), compared with the modular multiplication algorithms using two CSA.     

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.     

Hardware architecture design of block-matching and 3D-filtering denoising algorithm

Block-matching and 3D-filtering(BM3D) is a state of the art denoising algorithm for image/video,which takes full advantages of the spatial correlation and the temporal correlation of the video. The algorithm performance comes at the price of more similar blocks finding and filtering which bring high computation and memory access. Area, memory bandwidth and computation are the major bottlenecks to design a feasible architecture because of large frame size and search range. In this paper, we introduce a novel structure to increase data reuse rate and reduce the internal static-random-access-memory(SRAM) memory. Our target is to design a phase alternating line(PAL) or real-time processing chip of BM3 D. We propose an application specific integrated circuit(ASIC) architecture of BM3 D for a 720 × 576 BT656 PAL format. The feature of the chip is with 100 MHz system frequency and a 166-MHz 32-bit double data rate(DDR). When noise is σ = 25, we successfully realize real-time denoising and achieve about 10 d B peak signal to noise ratio(PSNR) advance just by one iteration of the BM3 D algorithm.     

Low-power and Low-cost Design of Survival Memory Unit for 1000Base-T Gigabit Ethernet Transceiver

Introduction The Gigabit Ethernet (GbE) on category-5unshielded twins pair (UTP) which corresponds tothe IEEE 802.3 ab1000 Base-T standard has grad-ually become the main trend of local area network(LAN). To take advantage of the additional cod-ing gain offered by the trellis-coded modulation(TCM) coding without using a maximum likeli-hood sequence estimation (MLSE) decoder, a deci-sion feedback sequence estimate[1](DFSE) decodercan be used[2-6]. Like the decision feedback equalizer …     

Optimization design of two-stage operational amplifier with frequency compensation via geometric programming

An optimization design technique to obtain global solution for a two-stage operational amplifier (op-amp) with frequency compensation is presented. This frequency compensation technique can adjust the equivalent resistance to guarantee that the phase margin is stable even though circumstance temperature varies. Geometric programming is used to optimize the component values and transistor dimensions. It is used in this analog integrated circuit design to calculate these parameters automatically. This globally optimal amplifier obtains minimum power while other specifications are fulfilled.     

Performance Analysis of Schemes in Fixed Two Frequency Reuse Relay Systems

An upsurge of interest in relay-augmented infrastructure-based networks has appeared in recent years. Radio resource management in such relay systems has great influence on the system performance. How to utilize the limited frequency resources efficiently in the system is a hot research topic. In this paper, performance of frequency reuse schemes has been studied in fixed relay systems. A novel scheme is achieved by modifying an existing one. Theoretical model is proposed for the performance analysis of two schemes. Both the theoretical analysis and simulation results show that the modified scheme outperforms the existing one not only in power consumption of mobile stations but also in cell carrier-to-interference ratio coverage.